Design of a Low-Power FPGA-Based Digital Filter for Audio Signal Processing Applications

Digital signal processing in embedded audio applications requires computationally efficient filter implementations that minimise power consumption, a particularly important constraint for battery-operated consumer electronics manufactured or targeted for Nigerian markets. This project designed and implemented a low-power finite impulse response digital filter on a Xilinx Spartan-6 FPGA development board, targeting audio signal processing applications at 44.1 kHz sample rate. A MATLAB-based filter design tool was used to calculate 64-tap FIR coefficients for a low-pass filter with a 3 dB cutoff at 8 kHz, intended to remove high-frequency noise from microphone-captured audio. The filter architecture was implemented in VHDL using a multiply-accumulate structure with 16-bit fixed-point arithmetic. Simulation was performed in ModelSim before synthesis on the target FPGA. Post-synthesis results showed a maximum clock frequency of 142 MHz, well above the required 44.1 kHz operating frequency, providing a 3,220x timing margin. The filter consumed 28 milliwatts of dynamic power at operational clock rate, meeting the sub-50 mW power budget. Stopband attenuation measured 72 dB, and passband ripple was below 0.15 dB. Total FPGA resource utilisation was 12 percent of Spartan-6 LUT capacity, leaving significant room for additional filter stages. The study recommends exploring a cascade of a low-pass and a high-pass filter to create a band-pass configuration for telephone-quality audio applications and testing on the Cyclone IV as an alternative low-cost FPGA platform.

Keywords: FPGA, FIR digital filter, VHDL, audio signal processing, low-power design